StallGuard result signed value?

[Ralf_1979]

Hi, i use the TMC262 with a parameter set for coolStep, i checked out with the eval board. As this works very well, i didn´t really took a closer look to the stallGuard result value.

So i did today, and it seems that the highest bit (bit 19, RD9) is alway '1'. This would mean, that the SG value is a sgined value; like the StallGuard threshold in the SGCSCON Register?
This wouldn´t make any sense to me, as it is described in the doc. with a range of 0...1023.

Do i have a SPI-Read Problem, or did i miss anything else?

[Ralf_1979]

Hm yeah, don´t start to think.
I used an older SPI-configuration with screwed clock polarity settings.

In case any ATMEL user´s find this topic:
CPHA and CPOL Bits in the SPCR register must be '1'
CPOL = Clock Polarity (1 = high on idle)
CPHA = Clock Phase (1 = sample on leading edge)


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