TMC423 N hold and Register hold bit setting?

[krunal_299]

I have confusion brtween these two bit setting in 423 datagram
1) Nhold bit
2) Register hold bit
Both freezes the Encoder hold registers on Interrupt ?
then what is the difference?
so pls explain it .

[TRINAMIC_BD]

The NHold bit controls encoder hold upon 0 channel active for each encoder separately.
The Common Hold bit freezes all encoders counters at once.

[krunal_299]

ok thank you very much !
so it means :
by Register hold register bit , i can freezes all the counter at any moment other than at interrupt .
is it ok?
Also pls let me know about any reference ciruit of TMC 423 .

[TRINAMIC_BD]

Currently there is no reference circuit available, which brings information in addition to the datasheet examples.

[krunal_299]

Ok no problem!
but whenever available pls let me know abt it.
I will be very thankful to your service.
Ans reply for following que:
by Register hold register bit , i can freezes all the counter at any moment other than at interrupt .
is it ok?

For encoder having high index pulse, what would be the setting of Npolarity and Ntrigger?
hope to have quik reply as earlier.
With heartest thnx.

[TRINAMIC_BD]

1: yes.
Npolarity=1 for positive encoder signal (pls. see manual page 16)
Ntrigger can be any.

[krunal_299]

ok
I have already reffered the datasheet .
But i was confused .
Ntrigger can be any.
So it does not make any difference to the event?

[krunal_299]

Oh dear !
I am still confused with Ntriggr bit setting.
Exactly what this bit control regarding to null channel event?

if i set Ntriggr bit for next N event then does it clear the couner at every 2 nd occurenc of N detection?

[TRINAMIC_BD]

I selects between clear once and clear always.

[krunal_299]

Thank u very much for your guidance!
If i clear this Ntrggr bit : then encoder counter register get cleared only once on null event after power on.
and if i set Ntrgr bit: then counter reg. get cleared on every occurence of null event.

is it right perception?

[TRINAMIC_BD]

You enable 0 clearing with bit Clear on N. Depending on N Trigger is becomes reset after one Clear event.